PVME4=B_0x0, PVME1=B_0x0, PVDE=B_0x0, PVME3=B_0x0, USV=B_0x0, PLS=B_0x0
Power control register 2
| PVDE | Programmable voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset. 0 (B_0x0): Programmable voltage detector disable. 1 (B_0x1): Programmable voltage detector enable. |
| PLS | Programmable voltage detector level selection. These bits select the voltage threshold detected by the programmable voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset. 0 (B_0x0): VPVD0 around 2.01V 1 (B_0x1): VPVD1 around 2.21V 2 (B_0x2): VPVD2 around 2.41V 3 (B_0x3): VPVD3 around 2.51V 4 (B_0x4): VPVD4 around 2.61V 5 (B_0x5): VPVD5 around 2.81V 6 (B_0x6): VPVD6 around 2.91V 7 (B_0x7): External input analog voltage PVD_IN (compared internally to VREFINT) |
| PVME1 | Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.21V 0 (B_0x0): PVM1 (VDDUSB monitoring vs. 1.21V threshold) disable. 1 (B_0x1): PVM1 (VDDUSB monitoring vs. 1.21V threshold) enable. |
| PVME3 | Peripheral voltage monitoring 3 enable: VDDA vs. 1.621V 0 (B_0x0): PVM3 (VDDA monitoring vs. 1.621V threshold) disable. 1 (B_0x1): PVM3 (VDDA monitoring vs. 1.621V threshold) enable. |
| PVME4 | Peripheral voltage monitoring 4 enable: VDDA vs. 1.861V 0 (B_0x0): PVM4 (VDDA monitoring vs. 1.861V threshold) disable. 1 (B_0x1): PVM4 (VDDA monitoring vs. 1.86 V threshold) enable. |
| USV | VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0 (B_0x0): VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply. 1 (B_0x1): VDDUSB is valid. |