CRCSMEN=B_0x0, SRAMSMEN=B_0x0, FLASHSMEN=B_0x0, TSCSMEN=B_0x0, DMA2SMEN=B_0x0, DMA1SMEN=B_0x0, RNGSMEN=B_0x0
AHB peripheral clock enable in Sleep/Stop mode register
| DMA1SMEN | DMA1 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DMA2SMEN | DMA2 and DMAMUX clock enable during Sleep mode Set and cleared by software. Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| FLASHSMEN | Flash memory interface clock enable during Sleep mode Set and cleared by software. This bit can be activated only when the flash memory is in power down mode. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| SRAMSMEN | SRAM clock enable during Sleep mode Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| CRCSMEN | CRC clock enable during Sleep mode Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RNGSMEN | RNG clock enable during Sleep and Stop mode Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TSCSMEN | TSC clock enable during Sleep and Stop mode Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |