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STMicroelectronics /STM32U031 /RCC /RCC_IOPSMENR

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Interpret as RCC_IOPSMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOASMEN 0 (B_0x0)GPIOBSMEN 0 (B_0x0)GPIOCSMEN 0 (B_0x0)GPIODSMEN 0 (B_0x0)GPIOESMEN 0 (B_0x0)GPIOFSMEN

GPIOASMEN=B_0x0, GPIODSMEN=B_0x0, GPIOESMEN=B_0x0, GPIOBSMEN=B_0x0, GPIOCSMEN=B_0x0, GPIOFSMEN=B_0x0

Description

I/O port in Sleep mode clock enable register

Fields

GPIOASMEN

I/O port A clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
GPIOBSMEN

I/O port B clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
GPIOCSMEN

I/O port C clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
GPIODSMEN

I/O port D clock enable during Sleep mode(1) Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
GPIOESMEN

I/O port E clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
GPIOFSMEN

I/O port F clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data