MSTR=B_0x0, RXONLY=B_0x0, BR=B_0x0, CPHA=B_0x0, LSBFIRST=B_0x0, CRCL=B_0x0, BIDIMODE=B_0x0, CRCEN=B_0x0, BIDIOE=B_0x0, SPE=B_0x0, CRCNEXT=B_0x0, SSM=B_0x0, CPOL=B_0x0
SPI control register 1
| CPHA | Clock phase Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. 0 (B_0x0): The first clock transition is the first data capture edge 1 (B_0x1): The second clock transition is the first data capture edge |
| CPOL | Clock polarity Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. 0 (B_0x0): CK to 0 when idle 1 (B_0x1): CK to 1 when idle |
| MSTR | Master selection Note: This bit should not be changed when communication is ongoing. 0 (B_0x0): Slave configuration 1 (B_0x1): Master configuration |
| BR | Baud rate control Note: These bits should not be changed when communication is ongoing. 0 (B_0x0): fPCLK/2 1 (B_0x1): fPCLK/4 2 (B_0x2): fPCLK/8 3 (B_0x3): fPCLK/16 4 (B_0x4): fPCLK/32 5 (B_0x5): fPCLK/64 6 (B_0x6): fPCLK/128 7 (B_0x7): fPCLK/256 |
| SPE | SPI enable Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page1954. 0 (B_0x0): Peripheral disabled 1 (B_0x1): Peripheral enabled |
| LSBFIRST | Frame format Note: 1. This bit should not be changed when communication is ongoing. Note: 2. This bit is not used in SPI TI mode. 0 (B_0x0): data is transmitted / received with the MSB first 1 (B_0x1): data is transmitted / received with the LSB first |
| SSI | Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in SPI TI mode. |
| SSM | Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in SPI TI mode. 0 (B_0x0): Software slave management disabled 1 (B_0x1): Software slave management enabled |
| RXONLY | Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0 (B_0x0): Full-duplex (Transmit and receive) 1 (B_0x1): Output disabled (Receive-only mode) |
| CRCL | CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 0 (B_0x0): 8-bit CRC length 1 (B_0x1): 16-bit CRC length |
| CRCNEXT | Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. 0 (B_0x0): Next transmit value is from Tx buffer. 1 (B_0x1): Next transmit value is from Tx CRC register. |
| CRCEN | Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 0 (B_0x0): CRC calculation disabled 1 (B_0x1): CRC calculation enabled |
| BIDIOE | Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. 0 (B_0x0): Output disabled (receive-only mode) 1 (B_0x1): Output enabled (transmit-only mode) |
| BIDIMODE | Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. 0 (B_0x0): 2-line unidirectional data mode selected 1 (B_0x1): 1-line bidirectional data mode selected |