STMicroelectronics /STM32U031 /SYSCFG /SYSCFG_CFGR2

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Interpret as SYSCFG_CFGR2

BKPL=B_0x0, BKPF=B_0x0, ECCL=B_0x0, PVDL=B_0x0, SPF=B_0x0, SPL=B_0x0, CCL=B_0x0

Description

SYSCFG configuration register 2

Fields

CCL	Cortex1<Default 1 Font>-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input. 0 (B_0x0): Cortex1<Default 1 Font>-M0+ LOCKUP output disconnected from TIM1/15/16 Break input 1 (B_0x1): Cortex1<Default 1 Font>-M0+ LOCKUP output connected to TIM1/15/16 Break input
SPL	SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input. 0 (B_0x0): SRAM1 parity error disconnected from TIM1/15/16 Break input 1 (B_0x1): SRAM1 parity error connected to TIM1/15/16 Break input
PVDL	PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. 0 (B_0x0): PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application. 1 (B_0x1): PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only.
ECCL	ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input. 0 (B_0x0): ECC error disconnected from TIM1/15/16 Break input 1 (B_0x1): ECC error connected to TIM1/15/16 Break input
BKPL	Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input. 0 (B_0x0): SRAM2 parity error disconnected from TIM1/15/16 Break input 1 (B_0x1): SRAM2 parity error connected to TIM1/15/16 Break input
BKPF	Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1. 0 (B_0x0): No SRAM2 parity error detected 1 (B_0x1): SRAM2 parity error detected
SPF	SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1. 0 (B_0x0): No SRAM1 parity error detected 1 (B_0x1): SRAM1 parity error detected

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