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STMicroelectronics /STM32U031 /SYSCFG /SYSCFG_SCSR

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Interpret as SYSCFG_SCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SRAM2ER)SRAM2ER 0 (B_0x0)SRAM2BSY

SRAM2BSY=B_0x0

Description

SYSCFG SRAM2 control and status register

Fields

SRAM2ER

SRAM2 erase Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation. Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.
SRAM2BSY

SRAM2 busy by erase operation

0 (B_0x0): No SRAM2 erase operation is ongoing

1 (B_0x1): SRAM2 erase operation is ongoing

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data