GC5C1=B_0x0, GC5C2=B_0x0, GC5C3=B_0x0
TIM1 capture/compare register 5
| CCR5 | Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output. |
| GC5C1 | Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of OC5REF on OC1REFC5 1 (B_0x1): OC1REFC is the logical AND of OC1REFC and OC5REF |
| GC5C2 | Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of OC5REF on OC2REFC 1 (B_0x1): OC2REFC is the logical AND of OC2REFC and OC5REF |
| GC5C3 | Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals. 0 (B_0x0): No effect of OC5REF on OC3REFC 1 (B_0x1): OC3REFC is the logical AND of OC3REFC and OC5REF |