STMicroelectronics /STM32U031 /TIM2 /TIM2_CCMR1_ALTERNATE1

Capture/Compare 1 selection

0 (B_0x0): CC1 channel is configured as output.

1 (B_0x1): CC1 channel is configured as input, IC1 is mapped on TI1.

2 (B_0x2): CC1 channel is configured as input, IC1 is mapped on TI2.

3 (B_0x3): CC1 channel is configured as input, IC1 is mapped on TRC.

Output compare 1 fast enable

0 (B_0x0): CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON.

1 (B_0x1): An active edge on the trigger input acts like a compare match on CC1 output.

Output compare 1 preload enable

0 (B_0x0): Preload register on TIMx_CCR1 disabled.

1 (B_0x1): Preload register on TIMx_CCR1 enabled.

OC1M[2:0]: Output compare 1 mode

0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.

1 (B_0x1): Set channel 1 to active level on match.

2 (B_0x2): Set channel 1 to inactive level on match.

3 (B_0x3): Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.

4 (B_0x4): Force inactive level - OC1REF is forced low.

5 (B_0x5): Force active level - OC1REF is forced high.

6 (B_0x6): PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTless thanTIMx_CCR1 else inactive.

7 (B_0x7): PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTless thanTIMx_CCR1 else active.

Output compare 1 clear enable

0 (B_0x0): OC1Ref is not affected by the ETRF input

1 (B_0x1): OC1Ref is cleared as soon as a High level is detected on ETRF input

Capture/Compare 2 selection

0 (B_0x0): CC2 channel is configured as output

1 (B_0x1): CC2 channel is configured as input, IC2 is mapped on TI2

2 (B_0x2): CC2 channel is configured as input, IC2 is mapped on TI1

3 (B_0x3): CC2 channel is configured as input, IC2 is mapped on TRC.

Output compare 2 fast enable

Output compare 2 preload enable

OC2M[2:0]: Output compare 2 mode

Output compare 2 clear enable

OC1M[3]

OC2M[3]