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STMicroelectronics /STM32U031 /TIM2 /TIM2_DCR

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Interpret as TIM2_DCR

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBA0 (B_0x0)DBL

DBL=B_0x0, DBA=B_0x0

Description

TIM2 DMA control register

Fields

DBA

DMA base address

0 (B_0x0): TIMx_CR1

1 (B_0x1): TIMx_CR2

2 (B_0x2): TIMx_SMCR
DBL

DMA burst length

0 (B_0x0): 1 transfer,

1 (B_0x1): 2 transfers,

2 (B_0x2): 3 transfers,

17 (B_0x11): 18 transfers.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data