URS=B_0x0, UIFREMAP=B_0x0, CEN=B_0x0, ARPE=B_0x0, DIR=B_0x0, CKD=B_0x0, UDIS=B_0x0, CMS=B_0x0, OPM=B_0x0
TIM3 control register 1
| CEN | Counter enable 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable 0 (B_0x0): UEV enabled. 1 (B_0x1): UEV disabled. |
| URS | Update request source 0 (B_0x0): Any of the following events generate an update interrupt or DMA request if enabled. 1 (B_0x1): Only counter overflow/underflow generates an update interrupt or DMA request if enabled. |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped at update event 1 (B_0x1): Counter stops counting at the next update event (clearing the bit CEN) |
| DIR | Direction 0 (B_0x0): Counter used as upcounter 1 (B_0x1): Counter used as downcounter |
| CMS | Center-aligned mode selection 0 (B_0x0): Edge-aligned mode. 1 (B_0x1): Center-aligned mode 1. 2 (B_0x2): Center-aligned mode 2. 3 (B_0x3): Center-aligned mode 3. |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIMx_ARR register is not buffered 1 (B_0x1): TIMx_ARR register is buffered |
| CKD | Clock division 0 (B_0x0): B_0x0 1 (B_0x1): B_0x1 2 (B_0x2): B_0x2 |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. 1 (B_0x1): Remapping enabled. |