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STMicroelectronics /STM32U031 /TIM3 /TIM3_OR1

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Interpret as TIM3_OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OCREF_CLR

OCREF_CLR=B_0x0

Description

TIM3 option register 1

Fields

OCREF_CLR

Ocref_clr source selection

0 (B_0x0): COMP1 output is connected to the OCREF_CLR input

1 (B_0x1): COMP2 output is connected to the OCREF_CLR input

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data