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STMicroelectronics /STM32U031 /TIM3 /TIM3_TISEL

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Interpret as TIM3_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL0 (B_0x0)TI2SEL0 (B_0x0)TI3SEL

TI3SEL=B_0x0, TI2SEL=B_0x0, TI1SEL=B_0x0

Description

TIM3 timer input selection register

Fields

TI1SEL

TI1[0] to TI1[15] input selection

0 (B_0x0): TIM3_CH1 input

1 (B_0x1): COMP1 output
TI2SEL

TI2[0] to TI2[15] input selection

0 (B_0x0): TIM3_CH2 input

1 (B_0x1): COMP2 output
TI3SEL

TI3[0] to TI3[15] input selection

0 (B_0x0): TIM3_CH3 input

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data