TIM6_SR

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Interpret as TIM6_SR

UIF=B_0x0

Description

TIM6 status register

Fields

UIF

Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS1=10 and UDIS1=10 in the TIMx_CR1 register.

0 (B_0x0): No update occurred.

1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated:

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