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STMicroelectronics /STM32U073 /RCC /RCC_APBSMENR2

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Interpret as RCC_APBSMENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SYSCFGSMEN 0 (B_0x0)TIM1SMEN 0 (B_0x0)SPI1SMEN 0 (B_0x0)USART1SMEN 0 (B_0x0)TIM15SMEN 0 (B_0x0)TIM16SMEN 0 (B_0x0)ADCSMEN

USART1SMEN=B_0x0, SPI1SMEN=B_0x0, TIM1SMEN=B_0x0, TIM16SMEN=B_0x0, SYSCFGSMEN=B_0x0, ADCSMEN=B_0x0, TIM15SMEN=B_0x0

Description

APB peripheral clock enable in Sleep/Stop mode register 2

Fields

SYSCFGSMEN

SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM1SMEN

TIM1 timer clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
SPI1SMEN

SPI1 clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
USART1SMEN

USART1 clock enable during Sleep and Stop modes Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM15SMEN

TIM15 timer clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
TIM16SMEN

TIM16 timer clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
ADCSMEN

ADC clock enable during Sleep mode Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data