KEYVALID=B_0x0, BUSY=B_0x0, RDERRF=B_0x0, WRERRF=B_0x0
AES status register
| RDERRF | Read error flag This bit is set when an unexpected read to the AES_DOUTR register occurred. When set RDERRF bit has no impact on the AES operations. The flag setting generates an interrupt if the RWEIE bit of the AES_IER register is set. The flag is cleared by setting the RWEIF bit of the AES_ICR register. 0 (B_0x0): No error 1 (B_0x1): Unexpected read to AES_DOUTR register occurred during computation or data input phase. |
| WRERRF | Write error flag This bit is set when an unexpected write to the AES_DINR register occurred. When set WRERRF bit has no impact on the AES operations. The flag setting generates an interrupt if the RWEIE bit of the AES_IER register is set. The flag is cleared by setting the RWEIF bit of the AES_ICR register. 0 (B_0x0): No error 1 (B_0x1): Unexpected write to AES_DINR register occurred during computation or data output phase. |
| BUSY | Busy This flag indicates whether AES is idle or busy. AES is flagged as idle when disabled (when EN is low) or when the last processing is completed. AES is flagged as busy when processing a block data, preparing a key (ECB or CBC decryption only). When GCM encryption is selected, this flag must be at zero before suspending current process to manage a higher-priority message. 0 (B_0x0): Idle 1 (B_0x1): Busy |
| KEYVALID | Key valid flag This bit is set by hardware when the key of size defined by KEYSIZE is loaded in AES_KEYRx key registers. The EN bit can only be set when KEYVALID is set. The key must be written in the key registers in the correct sequence, otherwise the KEIF flag is set and KEYVALID remains cleared. If set, KEIF must be cleared through the AES_ICR register, otherwise KEYVALID cannot be set. See the KEIF flag description for more details. For further information on key loading, refer to Section121.4.15: AES key registers. 0 (B_0x0): Key not valid 1 (B_0x1): Key valid |