ERRIE=B_0x0, SYNCOKIE=B_0x0, AUTOTRIMEN=B_0x0, CEN=B_0x0, SYNCWARNIE=B_0x0, ESYNCIE=B_0x0, SWSYNC=B_0x0
CRS control register
| SYNCOKIE | SYNC event OK interrupt enable 0 (B_0x0): SYNC event OK (SYNCOKF) interrupt disabled 1 (B_0x1): SYNC event OK (SYNCOKF) interrupt enabled |
| SYNCWARNIE | SYNC warning interrupt enable 0 (B_0x0): SYNC warning (SYNCWARNF) interrupt disabled 1 (B_0x1): SYNC warning (SYNCWARNF) interrupt enabled |
| ERRIE | Synchronization or trimming error interrupt enable 0 (B_0x0): Synchronization or trimming error (ERRF) interrupt disabled 1 (B_0x1): Synchronization or trimming error (ERRF) interrupt enabled |
| ESYNCIE | Expected SYNC interrupt enable 0 (B_0x0): Expected SYNC (ESYNCF) interrupt disabled 1 (B_0x1): Expected SYNC (ESYNCF) interrupt enabled |
| CEN | Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. 0 (B_0x0): Frequency error counter disabled 1 (B_0x1): Frequency error counter enabled |
| AUTOTRIMEN | Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section15.4.4 for more details. 0 (B_0x0): Automatic trimming disabled, TRIM bits can be adjusted by the user. 1 (B_0x1): Automatic trimming enabled, TRIM bits are read-only and under hardware control. |
| SWSYNC | Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. 0 (B_0x0): No action 1 (B_0x1): A software SYNC event is generated. |
| TRIM | HSI48 oscillator smooth trimming The default value of the HSI48 oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval. |