BUFEN=B_0x0, BIAS=B_0x0, MUX_SEG=B_0x0, VSEL=B_0x0, LCDEN=B_0x0, DUTY=B_0x0
LCD control register
| LCDEN | LCD controller enable This bit is set by software to enable the LCD controller/driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled, all COM and SEG pins are driven to VSS. 0 (B_0x0): LCD controller disabled 1 (B_0x1): LCD controller enabled |
| VSEL | Voltage source selection This bit determines the voltage source for the LCD. 0 (B_0x0): Internal source (voltage stepup converter) 1 (B_0x1): External source (VLCD pin) |
| DUTY | Duty selection These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. Others: Reserved 0 (B_0x0): Static duty 1 (B_0x1): 1/2 duty 2 (B_0x2): 1/3 duty 3 (B_0x3): 1/4 duty 4 (B_0x4): 1/8 duty |
| BIAS | Bias selector These bits determine the bias used. Value 11 is forbidden. 0 (B_0x0): Bias 1/4 1 (B_0x1): Bias 1/2 2 (B_0x2): Bias 1/3 |
| MUX_SEG | Mux segment enable This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with1SEG[31:28] or SEG[15:12]. See Section118.3.7. 0 (B_0x0): SEG pin multiplexing disabled 1 (B_0x1): SEG[31:28] multiplexed with SEG[43:40] |
| BUFEN | Voltage output buffer enable This bit is used to enable/disable the voltage output buffer for higher driving capability. 0 (B_0x0): Output buffer disabled 1 (B_0x1): Output buffer enabled |