BLINK=B_0x0, PON=B_0x0, HD=B_0x0, BLINKF=B_0x0, DIV=B_0x0, DEAD=B_0x0, CC=B_0x0, UDDIE=B_0x0, PS=B_0x0, SOFIE=B_0x0
LCD frame control register
| HD | High drive enable This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated. 0 (B_0x0): Permanent high drive disabled 1 (B_0x1): Permanent high drive enabled. When HD = 1, PON[2:0] must be programmed to 001. |
| SOFIE | Start of frame interrupt enable This bit is set and cleared by software. 0 (B_0x0): LCD start-of-frame interrupt disabled 1 (B_0x1): LCD start-of-frame interrupt enabled |
| UDDIE | Update display done interrupt enable This bit is set and cleared by software. 0 (B_0x0): LCD update display done interrupt disabled 1 (B_0x1): LCD update display done interrupt enabled |
| PON | Pulse ON duration These bits are written by software to define the pulse duration in terms of ck_ps pulses. A1short pulse leads to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast. Note that the pulse is never longer than one half prescaled LCD clock period. PON duration example with LCDCLK = 32.7681kHz and PS=0x03: 0 (B_0x0): 0 1s 1 (B_0x1): 244 1s 2 (B_0x2): 488 1s 3 (B_0x3): 782 1s 4 (B_0x4): 976 1s 5 (B_0x5): 1.22 ms 6 (B_0x6): 1.46 ms 7 (B_0x7): 1.71 ms |
| DEAD | Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate. … 0 (B_0x0): No dead time 1 (B_0x1): 1 phase period dead time 2 (B_0x2): 2 phase period dead time 7 (B_0x7): 7 phase period dead time |
| CC | Contrast control These bits specify one of the VLCD maximum voltages (independent of VDD). It ranges from12.60 V to 3.51V. Note: Refer to the datasheet for the VLCDx values. 0 (B_0x0): VLCD0 1 (B_0x1): VLCD1 2 (B_0x2): VLCD2 3 (B_0x3): VLCD3 4 (B_0x4): VLCD4 5 (B_0x5): VLCD5 6 (B_0x6): VLCD6 7 (B_0x7): VLCD7 |
| BLINKF | Blink frequency selection 0 (B_0x0): fLCD/8 1 (B_0x1): fLCD/16 2 (B_0x2): fLCD/32 3 (B_0x3): fLCD/64 4 (B_0x4): fLCD/128 5 (B_0x5): fLCD/256 6 (B_0x6): fLCD/512 7 (B_0x7): fLCD/1024 |
| BLINK | Blink mode selection 0 (B_0x0): Blink disabled 1 (B_0x1): Blink enabled on SEG[0], COM[0] (1 pixel) 2 (B_0x2): Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) 3 (B_0x3): Blink enabled on all SEGs and all COMs (all pixels) |
| DIV | DIV clock divider These bits are written by software to define the division factor of the DIV divider (see1Section118.3.2.) … 0 (B_0x0): ck_div = ck_ps/16 1 (B_0x1): ck_div = ck_ps/17 15 (B_0xF): ck_div = ck_ps/31 |
| PS | PS 16-bit prescaler These bits are written by software to define the division factor of the PS 16-bit prescaler. ck_ps = LCDCLK/(2PS[3:0]). See Section118.3.2. … 0 (B_0x0): ck_ps = LCDCLK 1 (B_0x1): ck_ps = LCDCLK/2 15 (B_0xF): ck_ps = LCDCLK/32768 |