SOF=B_0x0, ENS=B_0x0, RDY=B_0x0, FCRSF=B_0x0, UDR=B_0x0, UDD=B_0x0
LCD status register
| ENS | LCD enabled status This bit is set and cleared by hardware. It indicates the LCD controller status. Note: This bit is set immediately when LCDEN in LCD_CR goes from 0 to 1. On deactivation, it reflects the real LCD status. It becomes 0 at the end of the last displayed frame. 0 (B_0x0): LCD controller disabled 1 (B_0x1): LCD controller enabled |
| SOF | Start-of-frame flag This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to SOFC in LCD_CLR. The bit clear has priority over the set. 0 (B_0x0): No event 1 (B_0x1): Start-of-frame event occurred. An LCD SOF interrupt is generated if SOFIE is set. |
| UDR | Update display request Each time software modifies the LCD_RAM, it must set this bit to transfer the updated data to the second level buffer. This bit stays set until the end of the update. During this time, the LCD_RAM is write protected. When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, Note: only the LCD_DISPLAY of COM0 and COM1 are updated. Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1 0 (B_0x0): No effect 1 (B_0x1): Update display request |
| UDD | Update display done This bit is set by hardware. It is cleared by writing 1 to UDDC in LCD_CLR. The bit set has priority over the clear. Note: If the device is in Stop mode (PCLK not provided), UDD does not generate an interrupt even if UDDIE = 1. If the display is not enabled, the UDD interrupt never occurs. 0 (B_0x0): No event 1 (B_0x1): Update display request done. A UDD interrupt is generated if UDDIE = 1 in LCD_FCR. |
| RDY | Ready flag This bit is set and cleared by hardware. It indicates the status of the stepup converter. 0 (B_0x0): Not ready 1 (B_0x1): Stepup converter enabled and ready to provide the correct voltage |
| FCRSF | LCD frame control register synchronization flag This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register. 0 (B_0x0): LCD frame control register not yet synchronized 1 (B_0x1): LCD frame control register synchronized |