STMicroelectronics /STM32U083 /LPTIM3 /LPTIM3_ICR_INPUT

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Interpret as LPTIM3_ICR_INPUT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC1CF)CC1CF 0 (ARRMCF)ARRMCF 0 (EXTTRIGCF)EXTTRIGCF 0 (ARROKCF)ARROKCF 0 (UPCF)UPCF 0 (DOWNCF)DOWNCF 0 (UECF)UECF 0 (REPOKCF)REPOKCF 0 (CC2CF)CC2CF 0 (CC3CF)CC3CF 0 (CC4CF)CC4CF 0 (CC1OCF)CC1OCF 0 (CC2OCF)CC2OCF 0 (CC3OCF)CC3OCF 0 (CC4OCF)CC4OCF 0 (DIEROKCF)DIEROKCF

Description

LPTIM3 interrupt clear register [alternate]

Fields

CC1CF

Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.

ARRMCF

Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register

EXTTRIGCF

External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register

ARROKCF

Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register

UPCF

Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3.

DOWNCF

Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Refer to Section125.3.

UECF

Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.

REPOKCF

Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.

CC2CF

Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3.

CC3CF

Capture/compare 3 clear flag Writing 1 to this bit clears the CC3IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3.

CC4CF

Capture/compare 4 clear flag Writing 1 to this bit clears the CC4IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3.

CC1OCF

Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Refer to Section125.3.

CC2OCF

Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Refer to Section125.3.

CC3OCF

Capture/compare 3 over-capture clear flag Writing 1 to this bit clears the CC3OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 3 channels this bit is reserved. Refer to Section125.3.

CC4OCF

Capture/compare 4 over-capture clear flag Writing 1 to this bit clears the CC4OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 4 channels this bit is reserved. Refer to Section125.3.

DIEROKCF

Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.

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