I2C2EN=B_0x0, LPTIM2EN=B_0x0, USBEN=B_0x0, LPTIM1EN=B_0x0, LPTIM3EN=B_0x0, I2C4EN=B_0x0, I2C1EN=B_0x0, SPI2EN=B_0x0, USART3EN=B_0x0, USART4EN=B_0x0, I2C3EN=B_0x0, LPUART1EN=B_0x0, OPAMPEN=B_0x0, CRSEN=B_0x0, RTCAPBEN=B_0x0, LCDEN=B_0x0, SPI3EN=B_0x0, LPUART3EN=B_0x0, DAC1EN=B_0x0, WWDGEN=B_0x0, LPUART2EN=B_0x0, TIM7EN=B_0x0, TIM6EN=B_0x0, TIM3EN=B_0x0, PWREN=B_0x0, TIM2EN=B_0x0, USART2EN=B_0x0
APB peripheral clock enable register 1
| TIM2EN | TIM2 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM3EN | TIM3 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM6EN | TIM6 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| TIM7EN | TIM7 timer clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPUART2EN | LPUART2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LCDEN | LCD clock enable(1) Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RTCAPBEN | RTC APB clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| WWDGEN | WWDG clock enable Set by software to enable the window watchdog clock. Cleared by hardware system reset This bit can also be set by hardware if the WWDG_SW option bit is 0. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPUART3EN | LPUART3 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USBEN | USB clock enable(1) Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| SPI2EN | SPI2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| SPI3EN | SPI3 clock enable(1) Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| CRSEN | CRS clock enable(1) Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USART2EN | USART2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USART3EN | USART3 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| USART4EN | USART4 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPUART1EN | LPUART1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C1EN | I2C1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C2EN | I2C2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C3EN | I2C3 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| OPAMPEN | OPAMP clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C4EN | I2C4EN clock enable(1) Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPTIM3EN | LPTIM3 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PWREN | Power interface clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| DAC1EN | DAC1 interface clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPTIM2EN | LPTIM2 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LPTIM1EN | LPTIM1 clock enable Set and cleared by software. 0 (B_0x0): Disable 1 (B_0x1): Enable |