LPUART1SEL=B_0x0, ADCSEL=B_0x0, USART2SEL=B_0x0, CLK48SEL=B_0x0, USART1SEL=B_0x0, LPTIM2SEL=B_0x0, TIM15SEL=B_0x0, LPUART2SEL=B_0x0, LPUART3SEL=B_0x0, LPTIM1SEL=B_0x0, I2C1SEL=B_0x0, LPTIM3SEL=B_0x0, I2C3SEL=B_0x0, TIM1SEL=B_0x0
Peripherals independent clock configuration register
| USART1SEL | USART1 clock source selection This bitfield is controlled by software to select USART1 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| USART2SEL | USART2 clock source selection This bitfield is controlled by software to select USART2 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| LPUART3SEL | LPUART3 clock source selection(1) This bitfield is controlled by software to select LPUART3 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| LPUART2SEL | LPUART2 clock source selection This bitfield is controlled by software to select LPUART2 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| LPUART1SEL | LPUART1 clock source selection This bitfield is controlled by software to select LPUART1 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| I2C1SEL | I2C1 clock source selection This bitfield is controlled by software to select I2C1 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 |
| I2C3SEL | I2C3 clock source selection This bitfield is controlled by software to select I2C3 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): SYSCLK 2 (B_0x2): HSI16 |
| LPTIM1SEL | LPTIM1 clock source selection This bitfield is controlled by software to select LPTIM1 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): LSI 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| LPTIM2SEL | LPTIM2 clock source selection This bitfield is controlled by software to select LPTIM2 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): LSI 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| LPTIM3SEL | LPTIM3 clock source selection This bitfield is controlled by software to select LPTIM3 clock source as follows: 0 (B_0x0): PCLK 1 (B_0x1): LSI 2 (B_0x2): HSI16 3 (B_0x3): LSE |
| TIM1SEL | TIM1 clock source selection This bit is set and cleared by software. It selects TIM1 clock source as follows: 0 (B_0x0): TIMPCLK 1 (B_0x1): PLLQCLK |
| TIM15SEL | TIM15 clock source selection This bit is set and cleared by software. It selects TIM15 clock source as follows: 0 (B_0x0): TIMPCLK 1 (B_0x1): PLLQCLK |
| CLK48SEL | 481MHz clock source selection This bitfield is controlled by software to select the 481MHz clock source used by the USB FS and the RNG: 0 (B_0x0): No clock 1 (B_0x1): MSI 2 (B_0x2): PLLQCLK 3 (B_0x3): HSI48(1) |
| ADCSEL | ADCs clock source selection This bitfield is controlled by software to select the clock source for ADC: 0 (B_0x0): System clock 1 (B_0x1): PLLPCLK 2 (B_0x2): HSI16 |