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STMicroelectronics /STM32U083 /TSC /TSC_ICR

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Interpret as TSC_ICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EOAIC 0 (B_0x0)MCEIC

EOAIC=B_0x0, MCEIC=B_0x0

Description

TSC interrupt clear register

Fields

EOAIC

End of acquisition interrupt clear This bit is set by software to clear the end of acquisition flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect.

0 (B_0x0): No effect

1 (B_0x1): Clears the corresponding EOAF of the TSC_ISR register
MCEIC

Max count error interrupt clear This bit is set by software to clear the max count error flag and it is cleared by hardware when the flag is reset. Writing a 0 has no effect.

0 (B_0x0): No effect

1 (B_0x1): Clears the corresponding MCEF of the TSC_ISR register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data