STMicroelectronics /STM32U535 /GTZC1_TZSC /TZSC_SECCFGR3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TZSC_SECCFGR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MDF1SEC)MDF1SEC 0 (CORDICSEC)CORDICSEC 0 (FMACSEC)FMACSEC 0 (CRCSEC)CRCSEC 0 (TSCSEC)TSCSEC 0 (ICACHE_REGSEC)ICACHE_REGSEC 0 (DCACHE1_REGSEC)DCACHE1_REGSEC 0 (ADC1SEC)ADC1SEC 0 (DCMISEC)DCMISEC 0 (HASHSEC)HASHSEC 0 (RNGSEC)RNGSEC 0 (SDMMC1SEC)SDMMC1SEC 0 (OCTOSPI1_REGSEC)OCTOSPI1_REGSEC 0 (RAMCFGSEC)RAMCFGSEC 0 (GPU2DSEC)GPU2DSEC 0 (HSPI1_REGSEC)HSPI1_REGSEC

Description

TZSC secure configuration register 3

Fields

MDF1SEC

secure access mode for MDF1

CORDICSEC

secure access mode for CORDIC

FMACSEC

secure access mode for FMAC

CRCSEC

secure access mode for CRC

TSCSEC

secure access mode for TSC

ICACHE_REGSEC

secure access mode for ICACHE registers

DCACHE1_REGSEC

secure access mode for DCACHE1 registers

ADC1SEC

secure access mode for ADC1

DCMISEC

secure access mode for DCMI

HASHSEC

secure access mode for HASH

RNGSEC

secure access mode for RNG

SDMMC1SEC

secure access mode

OCTOSPI1_REGSEC

secure access mode for OCTOSPI1 registers

RAMCFGSEC

secure access mode for RAMCFG

GPU2DSEC

GPU2DSEC

HSPI1_REGSEC

HSPI1_REGSEC

Links

()