SRAM4PD=B_0x0, ULPMEN=B_0x0, SRAM5PD=B_0x0, LPMS=B_0x0, SRAM2PD=B_0x0, RRSB1=B_0x0, SRAM1PD=B_0x0, RRSB2=B_0x0
PWR control register 1
| LPMS | Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1 0 (B_0x0): Stop 0 mode 1 (B_0x1): Stop 1 mode 2 (B_0x2): Stop 2 mode 3 (B_0x3): Stop 3 mode |
| RRSB1 | SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. 0 (B_0x0): SRAM2 page1 content not retained in Stop 3 and Standby modes 1 (B_0x1): SRAM2 page1 content retained in Stop 3 and Standby modes |
| RRSB2 | SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. 0 (B_0x0): SRAM2 page2 content not retained in Stop3 and Standby modes 1 (B_0x1): SRAM2 page2 content retained in Stop 3 and Standby modes |
| ULPMEN | BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. 0 (B_0x0): BOR operating in continuous (normal) mode in Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) 1 (B_0x1): BOR operating in discontinuous (ultra-low power) mode in Stop 1, Stop 2, Stop 3 and Standby modes, and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) |
| SRAM1PD | SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. 0 (B_0x0): SRAM1 powered on 1 (B_0x1): SRAM1 powered off |
| SRAM2PD | SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. 0 (B_0x0): SRAM2 powered on 1 (B_0x1): SRAM2 powered off |
| SRAM4PD | SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. 0 (B_0x0): SRAM4 powered on 1 (B_0x1): SRAM4 powered off |
| SRAM5PD | SRAM5 power down This bit is used to reduce the consumption by powering off the SRAM5. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. 0 (B_0x0): SRAM5 powered on 1 (B_0x1): SRAM5 powered off |