STMicroelectronics /STM32U575 /ADC1 /ADC_CFGR1

Data management configuration This bit is set and cleared by software to select how the ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): Regular conversion data stored in DR only

1 (B_0x1): DMA One -shot mode selected

2 (B_0x2): MDF mode selected

3 (B_0x3): DMA Circular mode selected

Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): 14 bits

1 (B_0x1): 12 bits

2 (B_0x2): 10 bits

3 (B_0x3): 8bits

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Refer to the ADC external trigger for regular channels in signals for details on trigger mapping. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): adc_ext_trg0

1 (B_0x1): adc_ext_trg1

External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software)

1 (B_0x1): Hardware trigger detection on the rising edge

2 (B_0x2): Hardware trigger detection on the falling edge

3 (B_0x3): Hardware trigger detection on both the rising and falling edges

Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected.

1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Single conversion mode

1 (B_0x1): Continuous conversion mode

Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode… Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): Auto-delayed conversion mode off

1 (B_0x1): Auto-delayed conversion mode on

Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Discontinuous mode for regular channels disabled

1 (B_0x1): Discontinuous mode for regular channels enabled

Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): 1 channel

1 (B_0x1): 2 channels

7 (B_0x7): 8 channels

Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

0 (B_0x0): Discontinuous mode on injected channels disabled

1 (B_0x1): Discontinuous mode on injected channels enabled

Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): Analog watchdog 1 enabled on all channels

1 (B_0x1): Analog watchdog 1 enabled on a single channel

Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Analog watchdog 1 disabled on regular channels

1 (B_0x1): Analog watchdog 1 enabled on regular channels

Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

0 (B_0x0): Analog watchdog 1 disabled on injected channels

1 (B_0x1): Analog watchdog 1 enabled on injected channels

Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).

0 (B_0x0): Automatic injected group conversion disabled

1 (B_0x1): Automatic injected group conversion enabled

Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. … Others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): ADC analog input channel-0 monitored by AWD1

1 (B_0x1): ADC analog input channel-1 monitored by AWD1

19 (B_0x13): ADC analog input channel-19 monitored by AWD1