STMicroelectronics /STM32U575 /ADC1 /ADC_JSQR

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Interpret as ADC_JSQR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)JL0 (B_0x0)JEXTSEL0 (B_0x0)JEXTEN 0JSQ10JSQ20JSQ30JSQ4

JL=B_0x0, JEXTSEL=B_0x0, JEXTEN=B_0x0

Description

ADC injected sequence register

Fields

JL

Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

0 (B_0x0): 1 conversion

1 (B_0x1): 2 conversions

2 (B_0x2): 3 conversions

3 (B_0x3): 4 conversions

JEXTSEL

External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: … Refer to the ADC external trigger for injected channels in internal signals for details on trigger mapping. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

0 (B_0x0): adc_jext_trg0

1 (B_0x1): adc_jext_trg1

JEXTEN

External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software)

1 (B_0x1): Hardware trigger detection on the rising edge

2 (B_0x2): Hardware trigger detection on the falling edge

3 (B_0x3): Hardware trigger detection on both the rising and falling edges

JSQ1

1st conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

JSQ2

2nd conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

JSQ3

3rd conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

JSQ4

4th conversion in the injected sequence These bits are written by software with the channel number (0…19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.

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