TXDMAEN=B_0x0, UDRCFG=B_0x0, DSIZE=B_0x0, BPASS=B_0x0, MBR=B_0x0, RXDMAEN=B_0x0, CRCEN=B_0x0, FTHLV=B_0x0
SPI configuration register 1
| DSIZE | number of bits in at single SPI data frame … Note: Maximum data size can be limited up to 16-bits at some instances. At instances with limited set of features, DSIZE2:0] bits are reserved and must be kept at reset state. DSIZE[4:3] bits then control next settings of data size: 00xxx: 8-bits 01xxx: 16-bits 10xxx: 24-bits 11xxx: 32-bits. 0 (B_0x0): not used 1 (B_0x1): not used 2 (B_0x2): not used 3 (B_0x3): 4-bits 4 (B_0x4): 5-bits 5 (B_0x5): 6-bits 6 (B_0x6): 7-bits 7 (B_0x7): 8-bits 29 (B_0x1D): 30-bits 30 (B_0x1E): 31-bits 31 (B_0x1F): 32-bits |
| FTHLV | FIFO threshold level Defines number of data frames at single data packet. Size of the packet should not exceed 1/2 of FIFO space. SPI interface is more efficient if configured packet sizes are aligned with data register access parallelism: If SPI data register is accessed as a 16-bit register and DSIZE ¤ 8 bit, better to select FTHLV = 2, 4, 6. If SPI data register is accessed as a 32-bit register and DSIZE> 8 bit, better to select FTHLV = 2, 4, 6, while if DSIZE ¤ 8bit, better to select FTHLV = 4, 8, 12. Note: FTHLV[3:2] bits are reserved at instances with limited set of features 0 (B_0x0): 1-data 1 (B_0x1): 2-data 2 (B_0x2): 3-data 3 (B_0x3): 4-data 4 (B_0x4): 5-data 5 (B_0x5): 6-data 6 (B_0x6): 7-data 7 (B_0x7): 8-data 8 (B_0x8): 9-data 9 (B_0x9): 10-data 10 (B_0xA): 11-data 11 (B_0xB): 12-data 12 (B_0xC): 13-data 13 (B_0xD): 14-data 14 (B_0xE): 15-data 15 (B_0xF): 16-data |
| UDRCFG | behavior of slave transmitter at underrun condition For more details see underrun condition. 0 (B_0x0): slave sends a constant pattern defined by the user at the SPI_UDRDR register 1 (B_0x1): Slave repeats lastly received data from master. When slave is configured at transmit only mode (COMM[1:0]=01), all zeros pattern is repeated. |
| RXDMAEN | Rx DMA stream enable 0 (B_0x0): Rx-DMA disabled 1 (B_0x1): Rx-DMA enabled |
| TXDMAEN | Tx DMA stream enable 0 (B_0x0): Tx DMA disabled 1 (B_0x1): Tx DMA enabled |
| CRCSIZE | length of CRC frame to be transacted and compared Most significant bits are taken into account from polynomial calculation when CRC result is transacted or compared. The length of the polynomial is not affected by this setting. … The value must be set equal or multiply of data size (DSIZE[4:0]). Its maximum size corresponds to DSIZE maximum at the instance. Note: The most significant bit at CRCSIZE bit field is reserved at the peripheral instances where data size is limited to 16-bit. 3 (B_0x3): 4-bits 4 (B_0x4): 5-bits 5 (B_0x5): 6-bits 6 (B_0x6): 7-bits 7 (B_0x7): 8-bits 29 (B_0x1D): 30-bits 30 (B_0x1E): 31-bits 31 (B_0x1F): 32-bits |
| CRCEN | hardware CRC computation enable 0 (B_0x0): CRC calculation disabled 1 (B_0x1): CRC calculation enabled |
| MBR | master baud rate prescaler setting Note: MBR setting is considered at slave working at TI mode, too (see mode). 0 (B_0x0): SPI master clock/2 1 (B_0x1): SPI master clock/4 2 (B_0x2): SPI master clock/8 3 (B_0x3): SPI master clock/16 4 (B_0x4): SPI master clock/32 5 (B_0x5): SPI master clock/64 6 (B_0x6): SPI master clock/128 7 (B_0x7): SPI master clock/256 |
| BPASS | bypass of the prescaler at master baud rate clock generator 0 (B_0x0): bypass is disabled 1 (B_0x1): bypass is enabled |