STMicroelectronics /STM32U575 /SPI1 /SPI_SR

Rx-Packet available RXP flag is changed by hardware. It monitors number of overall data currently available at RxFIFO if SPI is enabled. It has to be checked once a data packet is completely read out from RxFIFO.

0 (B_0x0): RxFIFO is empty or a not complete data packet is received

1 (B_0x1): RxFIFO contains at least 1 data packet

Tx-Packet space available TXP flag is changed by hardware. It monitors overall space currently available at TxFIFO no matter if SPI is enabled or not. It has to be checked once a complete data packet is stored at TxFIFO.

0 (B_0x0): there is not enough space to locate next data packet at TxFIFO

1 (B_0x1): TxFIFO has enough free location to host 1 data packet

duplex packet DXP flag is set whenever both TXP and RXP flags are set regardless SPI mode.

0 (B_0x0): TxFIFO is Full and/or RxFIFO is Empty

1 (B_0x1): both TxFIFO has space for write and RxFIFO contains for read a single packet at least

end of transfer EOT is set by hardware as soon as a full transfer is complete, that is when TSIZE number of data have been transmitted and/or received on the SPI. EOT is cleared by software write 1 to EOTC bit at SPI_IFCR. EOT flag triggers an interrupt if EOTIE bit is set. If DXP flag is used until TXTF flag is set and DXPIE is cleared, EOT can be used to download the last packets contained into RxFIFO in one-shot. In master, EOT event terminates the data transaction and handles SS output optionally. When CRC is applied, the EOT event is extended over the CRC frame transaction. To restart the internal state machine properly, SPI is strongly suggested to be disabled and re-enabled before next transaction starts despite its setting is not changed.

0 (B_0x0): transfer is on-going or not started

1 (B_0x1): transfer complete

transmission transfer filled TXTF is set by hardware as soon as all of the data packets in a transfer have been submitted for transmission by application software or DMA, that is when TSIZE number of data have been pushed into the TxFIFO. This bit is cleared by software write 1 to TXTFC bit at SPI_IFCR TXTF flag triggers an interrupt if TXTFIE bit is set. TXTF setting clears the TXPIE and DXPIE masks so to off-load application software from calculating when to disable TXP and DXP interrupts.

0 (B_0x0): upload of TxFIFO is on-going or not started

1 (B_0x1): TxFIFO upload is finished

underrun at slave transmission mode This bit is cleared by writing 1 to UDRC bit at SPI_IFCR Note: UDR flag applies to Slave mode only

0 (B_0x0): no underrun

1 (B_0x1): underrun detected

overrun This bit is cleared by writing 1 to OVRC bit at SPI_IFCR

0 (B_0x0): no overrun

1 (B_0x1): overrun detected

CRC error This bit is cleared by writing 1 to CRCEC bit at SPI_IFCR

0 (B_0x0): no CRC error

1 (B_0x1): CRC error detected

TI frame format error This bit is cleared by writing 1 to TIFREC bit at SPI_IFCR

0 (B_0x0): no TI Frame Error

1 (B_0x1): TI frame error detected

mode fault This bit is cleared by writing 1 to MODFC bit at SPI_IFCR

0 (B_0x0): no mode fault

1 (B_0x1): mode fault detected. When MODF is set, SPE and IOLOCK bits at SPI_CR1 register are reset and their setting is blocked.

suspension status In Master mode, SUSP is set by hardware either as soon as the current frame is completed after CSUSP request is done or at master automatic suspend receive mode (MASRX bit is set at SPI_CR1 register) on RxFIFO full condition. SUSP generates an interrupt when EOTIE is set. This bit has to be cleared prior SPI is disabled by writing 1 to SUSPC bit at SPI_IFCR.

0 (B_0x0): SPI not suspended (Master mode active or other mode).

1 (B_0x1): Master mode is suspended (current frame completed).

TxFIFO transmission complete The flag behavior depends on TSIZE setting. When TSIZE=0 the TXC is changed by hardware exclusively and it raises each time the TxFIFO becomes empty and there is no activity on the bus. If TSIZE <>0 there is no specific reason to monitor TXC as it just copies the EOT flag value including its software clearing. The TXC generates an interrupt when EOTIE is set.

0 (B_0x0): current data transaction is still ongoing, data is available in TxFIFO or last frame transmission is on going.

1 (B_0x1): last TxFIFO frame transmission complete

RxFIFO packing level When RXWNE=0 and data size is set up to 16-bit, the value gives number of remaining data frames persisting at RxFIFO. Note: (*): Optional value when data size is set up to 8-bit only. When data size is greater than 16-bit, these bits are always read as 00. In that consequence, the single data frame received at the FIFO cannot be detected neither by RWNE nor by RXPLVL bits if data size is set from 17 to 24 bits. The user then must apply other methods like TSIZE>0 or FTHLV=0.

0 (B_0x0): no next frame is available at RxFIFO

1 (B_0x1): 1 frame is available

2 (B_0x2): 2 frames are available*

3 (B_0x3): 3 frames are available*

RxFIFO word not empty Note: This bit value does not depend on DSIZE setting and keeps together with RXPLVL[1:0] information about RxFIFO occupancy by residual data.

0 (B_0x0): less than four bytes of RxFIFO space is occupied by data

1 (B_0x1): at least four bytes of RxFIFO space is occupied by data

number of data frames remaining in current TSIZE session The value is not quite reliable when traffic is ongoing on bus or during autonomous operation at low-power mode. Note: CTSIZE[15:0] bits are not available at instances with limited set of features