BKCMP2P=B_0x0, BKCMP8E=B_0x0, BKCMP4E=B_0x0, BKCMP1P=B_0x0, BKCMP1E=B_0x0, BKCMP7E=B_0x0, BKCMP2E=B_0x0, BKCMP5E=B_0x0, ETRSEL=B_0x0, BKINP=B_0x0, BKCMP6E=B_0x0, BKCMP3E=B_0x0, BKCMP4P=B_0x0, BKINE=B_0x0, BKCMP3P=B_0x0
TIM1 alternate function option register 1
| BKINE | TIMx_BKIN input enable This bit enables the TIMx_BKIN alternate function input for the timerâs tim_brk input. TIMx_BKIN input is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): TIMx_BKIN input disabled 1 (B_0x1): TIMx_BKIN input enabled |
| BKCMP1E | tim_brk_cmp1 enable This bit enables the tim_brk_cmp1 for the timerâs tim_brk input. tim_brk_cmp1 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp1 input disabled 1 (B_0x1): tim_brk_cmp1 input enabled |
| BKCMP2E | tim_brk_cmp2 enable This bit enables the tim_brk_cmp2 for the timerâs tim_brk input. tim_brk_cmp2 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp2 input disabled 1 (B_0x1): tim_brk_cmp2 input enabled |
| BKCMP3E | tim_brk_cmp3 enable This bit enables the tim_brk_cmp3 for the timerâs tim_brk input. tim_brk_cmp3 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp3 input disabled 1 (B_0x1): tim_brk_cmp3 input enabled |
| BKCMP4E | tim_brk_cmp4 enable This bit enables the tim_brk_cmp4 for the timerâs tim_brk input. tim_brk_cmp4 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp4 input disabled 1 (B_0x1): tim_brk_cmp4 input enabled |
| BKCMP5E | tim_brk_cmp5 enable This bit enables the tim_brk_cmp5 for the timerâs tim_brk input. tim_brk_cmp5 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp5 input disabled 1 (B_0x1): tim_brk_cmp5 input enabled |
| BKCMP6E | tim_brk_cmp6 enable This bit enables the tim_brk_cmp6 for the timerâs tim_brk input. tim_brk_cmp6 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp6 input disabled 1 (B_0x1): tim_brk_cmp6 input enabled |
| BKCMP7E | tim_brk_cmp7 enable This bit enables the tim_brk_cmp7 for the timerâs tim_brk input. tim_brk_cmp7 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp7 input disabled 1 (B_0x1): tim_brk_cmp7 input enabled |
| BKCMP8E | tim_brk_cmp8 enable This bit enables the tim_brk_cmp8 for the timerâs tim_brk input. tim_brk_cmp8 output is 'ORedâ with the other tim_brk sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp8 input disabled 1 (B_0x1): tim_brk_cmp8 input enabled |
| BKINP | TIMx_BKIN input polarity This bit selects the TIMx_BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): TIMx_BKIN input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) 1 (B_0x1): TIMx_BKIN input polarity is inverted (active high if BKP = 0, active low if BKP = 1) |
| BKCMP1P | tim_brk_cmp1 input polarity This bit selects the tim_brk_cmp1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp1 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) 1 (B_0x1): tim_brk_cmp1 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) |
| BKCMP2P | tim_brk_cmp2 input polarity This bit selects the tim_brk_cmp2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp2 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) 1 (B_0x1): tim_brk_cmp2 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) |
| BKCMP3P | tim_brk_cmp3 input polarity This bit selects the tim_brk_cmp3 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp3 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) 1 (B_0x1): tim_brk_cmp3 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) |
| BKCMP4P | tim_brk_cmp4 input polarity This bit selects the tim_brk_cmp4 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_brk_cmp4 input polarity is not inverted (active low if BKP = 0, active high if BKP = 1) 1 (B_0x1): tim_brk_cmp4 input polarity is inverted (active high if BKP = 0, active low if BKP = 1) |
| ETRSEL | etr_in source selection These bits select the etr_in input source. … Refer to for product specific implementation. Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 0 (B_0x0): tim_etr0: TIMx_ETR input 1 (B_0x1): tim_etr1 15 (B_0xF): tim_etr15 |