STMicroelectronics /STM32U599 /DSI /DSI_DPDL0BCR

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Interpret as DSI_DPDL0BCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BC

BC=B_0x0

Description

DSI D-PHY data lane 0 band control register

Fields

BC

Band control This field selects the frequency band used by the D-PHY. Others: Reserved

0 (B_0x0): 80 to 100 MHz

1 (B_0x1): 100 to 120 MHz

2 (B_0x2): 120 to 160 MHz

3 (B_0x3): 160 to 200 MHz

4 (B_0x4): 200 to 240 MHz

5 (B_0x5): 240 to 320 MHz

6 (B_0x6): 320 to 390 MHz

7 (B_0x7): 390 to 450 MHz

8 (B_0x8): 450 to 510 MHz

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