BK_ECC=B_0x0, ECCIE=B_0x0
FLASH ECC register
| ADDR_ECC | ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given by bank from address 0x0 0000 to 0x1F FFF0. |
| BK_ECC | ECC fail bank This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection. 0 (B_0x0): Bank 1 1 (B_0x1): Bank 2 |
| SYSF_ECC | System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. |
| ECCIE | ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. 0 (B_0x0): ECCC interrupt disabled 1 (B_0x1): ECCC interrupt enabled. |
| ECCC | ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. |
| ECCD | ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. |