SRAM/NOR-Flash chip-select timing register for bank 2
| ADDSET | Address setup phase duration |
| ADDHLD | Address-hold phase duration |
| DATAST | Data-phase duration |
| BUSTURN | Bus turnaround phase duration |
| CLKDIV | Clock divide ratio (for FMC_CLK signal) |
| DATLAT | Data latency for synchronous memory |
| ACCMOD | Access mode |
| DATAHLD | Data hold phase duration |