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STMicroelectronics /STM32U599 /GTZC2_MPCBB4 /MPCBB4_SECCFGR0

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Interpret as MPCBB4_SECCFGR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SEC0)SEC0 0 (SEC1)SEC1 0 (SEC2)SEC2 0 (SEC3)SEC3 0 (SEC4)SEC4 0 (SEC5)SEC5 0 (SEC6)SEC6 0 (SEC7)SEC7 0 (SEC8)SEC8 0 (SEC9)SEC9 0 (SEC10)SEC10 0 (SEC11)SEC11 0 (SEC12)SEC12 0 (SEC13)SEC13 0 (SEC14)SEC14 0 (SEC15)SEC15 0 (SEC16)SEC16 0 (SEC17)SEC17 0 (SEC18)SEC18 0 (SEC19)SEC19 0 (SEC20)SEC20 0 (SEC21)SEC21 0 (SEC22)SEC22 0 (SEC23)SEC23 0 (SEC24)SEC24 0 (SEC25)SEC25 0 (SEC26)SEC26 0 (SEC27)SEC27 0 (SEC28)SEC28 0 (SEC29)SEC29 0 (SEC30)SEC30 0 (SEC31)SEC31

Description

MPCBB security configuration for super-block 0 register

Fields

SEC0

SEC0
SEC1

SEC1
SEC2

SEC2
SEC3

SEC3
SEC4

SEC4
SEC5

SEC5
SEC6

SEC6
SEC7

SEC7
SEC8

SEC8
SEC9

SEC9
SEC10

SEC10
SEC11

SEC11
SEC12

SEC12
SEC13

SEC13
SEC14

SEC14
SEC15

SEC15
SEC16

SEC16
SEC17

SEC17
SEC18

SEC18
SEC19

SEC19
SEC20

SEC20
SEC21

SEC21
SEC22

SEC22
SEC23

SEC23
SEC24

SEC24
SEC25

SEC25
SEC26

SEC26
SEC27

SEC27
SEC28

SEC28
SEC29

SEC29
SEC30

SEC30
SEC31

SEC31

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data