MTYP=B_0x0, DLYBYP=B_0x0, CSHT=B_0x0, FRCK=B_0x0, CKMODE=B_0x0
HSPI device configuration register 1
| CKMODE | Mode 0/Mode 3 This bit indicates the level taken by the CLK between commands (when nCSÂ =Â 1). 0 (B_0x0): CLK must stay low while nCS is high (chip-select released). This is referred to as Mode 0. 1 (B_0x1): CLK must stay high while nCS is high (chip-select released). This is referred to as Mode 3. |
| FRCK | Free running clock This bit configures the free running clock. 0 (B_0x0): CLK is not free running. 1 (B_0x1): CLK is free running (always provided). |
| DLYBYP | Delay block bypass 0 (B_0x0): The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the HSPI). 1 (B_0x1): The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block. |
| CSHT | Chip-select high time CSHTÂ +Â 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. … 63: nCS stays high for at least 64 cycles between external device commands. Note: When the extended CSHT timeout feature is not supported, CSHT[5:3] are reserved and the number of cycles is limited to eight (refer to implementation). 0 (B_0x0): nCS stays high for at least 1 cycle between external device commands. 1 (B_0x1): nCS stays high for at least 2 cycles between external device commands. |
| DEVSIZE | Device size This field defines the size of the external device using the following formula: Number of bytes in device = 2[DEVSIZE+1]. DEVSIZE+1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4Â Gbytes (addressed using 32-bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256Â Mbytes. In Regular-command mode, if DMMÂ =Â 1, DEVSIZE[4:0] indicates the total capacity of the two devices together. |
| MTYP | Memory type This bit indicates the type of memory to be supported. Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron. Others: Reserved 0 (B_0x0): Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual- and Single-SPI modes 1 (B_0x1): Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual-, and Single-SPI modes 2 (B_0x2): Standard mode 3 (B_0x3): Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal-, Quad-, Dual-, and Single-SPI with dedicated address mapping. 4 (B_0x4): HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected. 5 (B_0x5): HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used. |