ABSIZE=B_0x0, ADSIZE=B_0x0, IDTR=B_0x0, ABMODE=B_0x0, DQSE=B_0x0, ADDTR=B_0x0, ISIZE=B_0x0, IMODE=B_0x0, DDTR=B_0x0, DMODE=B_0x0, ABDTR=B_0x0, ADMODE=B_0x0
HSPI wrap communication configuration register
| IMODE | Instruction mode This field defines the instruction phase mode of operation. 101-111: Reserved 0 (B_0x0): No instruction 1 (B_0x1): Instruction on a single line 2 (B_0x2): Instruction on two lines 3 (B_0x3): Instruction on four lines 4 (B_0x4): Instruction on eight lines |
| IDTR | Instruction double transfer rate This bit sets the DTR mode for the instruction phase. 0 (B_0x0): DTR mode disabled for instruction phase 1 (B_0x1): DTR mode enabled for instruction phase |
| ISIZE | Instruction size This field defines instruction size. 0 (B_0x0): 8-bit instruction 1 (B_0x1): 16-bit instruction 2 (B_0x2): 24-bit instruction 3 (B_0x3): 32-bit instruction |
| ADMODE | Address mode This field defines the address phase mode of operation. 101-111: Reserved 0 (B_0x0): No address 1 (B_0x1): Address on a single line 2 (B_0x2): Address on two lines 3 (B_0x3): Address on four lines 4 (B_0x4): Address on eight lines |
| ADDTR | Address double transfer rate This bit sets the DTR mode for the address phase. 0 (B_0x0): DTR mode disabled for address phase 1 (B_0x1): DTR mode enabled for address phase |
| ADSIZE | Address size This field defines address size. 0 (B_0x0): 8-bit address 1 (B_0x1): 16-bit address 2 (B_0x2): 24-bit address 3 (B_0x3): 32-bit address |
| ABMODE | Alternate-byte mode This field defines the alternate byte phase mode of operation. 0 (B_0x0): No alternate bytes 1 (B_0x1): Alternate bytes on a single line 2 (B_0x2): Alternate bytes on two lines 3 (B_0x3): Alternate bytes on four lines 4 (B_0x4): Alternate bytes on eight lines 5 (B_0x5): Alternate bytes on 16 lines |
| ABDTR | Alternate bytes double transfer rate This bit sets the DTR mode for the alternate bytes phase. 0 (B_0x0): DTR mode disabled for alternate bytes phase 1 (B_0x1): DTR mode enabled for alternate bytes phase |
| ABSIZE | Alternate bytes size This bit defines alternate bytes size. 0 (B_0x0): 8-bit alternate bytes 1 (B_0x1): 16-bit alternate bytes 2 (B_0x2): 24-bit alternate bytes 3 (B_0x3): 32-bit alternate bytes |
| DMODE | Data mode This field defines the data phase mode of operation. 101; Data on 16 lines 110-111: Reserved 0 (B_0x0): No data 1 (B_0x1): Data on a single line 2 (B_0x2): Data on two lines 3 (B_0x3): Data on four lines 4 (B_0x4): Data on eight lines |
| DDTR | Data double transfer rate This bit sets the DTR mode for the data phase. 0 (B_0x0): DTR mode disabled for data phase 1 (B_0x1): DTR mode enabled for data phase |
| DQSE | DQS enable This bit enables the data strobe management. 0 (B_0x0): DQS disabled 1 (B_0x1): DQS enabled |