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STMicroelectronics /STM32U599 /LTDC /LTDC_SRCR

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Interpret as LTDC_SRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IMR 0 (B_0x0)VBR

IMR=B_0x0, VBR=B_0x0

Description

LTDC shadow reload configuration register

Fields

IMR

immediate reload This bit is set by software and cleared only by hardware after reload.

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded immediately.
VBR

vertical blanking reload This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).

0 (B_0x0): no effect

1 (B_0x1): The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data