LPDMA1EN=B_0x0, GTZC2EN=B_0x0, DAC1EN=B_0x0, SRAM4EN=B_0x0, ADF1EN=B_0x0, ADC4EN=B_0x0, LPGPIO1EN=B_0x0, PWREN=B_0x0
RCC AHB3 peripheral clock enable register
| LPGPIO1EN | LPGPIO1 enable This bit is set and cleared by software. 0 (B_0x0): LPGPIO1 clock disabled 1 (B_0x1): LPGPIO1 clock enabled |
| PWREN | PWR clock enable This bit is set and cleared by software. 0 (B_0x0): PWR clock disabled 1 (B_0x1): PWR clock enabled |
| ADC4EN | ADC4 clock enable This bit is set and cleared by software. 0 (B_0x0): ADC4 clock disabled 1 (B_0x1): ADC4 clock enabled |
| DAC1EN | DAC1 clock enable This bit is set and cleared by software. 0 (B_0x0): DAC1 clock disabled 1 (B_0x1): DAC1 clock enabled |
| LPDMA1EN | LPDMA1 clock enable This bit is set and cleared by software. 0 (B_0x0): LPDMA1 clock disabled 1 (B_0x1): LPDMA1 clock enabled |
| ADF1EN | ADF1 clock enable This bit is set and cleared by software. 0 (B_0x0): ADF1 clock disabled 1 (B_0x1): ADF1 clock enabled |
| GTZC2EN | GTZC2 clock enable This bit is set and cleared by software. 0 (B_0x0): GTZC2 clock disabled 1 (B_0x1): GTZC2 clock enabled |
| SRAM4EN | SRAM4 clock enable This bit is set and reset by software. 0 (B_0x0): SRAM4 clock disabled 1 (B_0x1): SRAM4 clock enabled |