TIM5EN=B_0x0, TIM4EN=B_0x0, TIM7EN=B_0x0, USART3EN=B_0x0, CRSEN=B_0x0, I2C1EN=B_0x0, UART5EN=B_0x0, TIM2EN=B_0x0, I2C2EN=B_0x0, WWDGEN=B_0x0, USART6EN=B_0x0, TIM3EN=B_0x0, UART4EN=B_0x0, TIM6EN=B_0x0, SPI2EN=B_0x0, USART2EN=B_0x0
RCC APB1 peripheral clock enable register 1
| TIM2EN | TIM2 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM2 clock disabled 1 (B_0x1): TIM2 clock enabled |
| TIM3EN | TIM3 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM3 clock disabled 1 (B_0x1): TIM3 clock enabled |
| TIM4EN | TIM4 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM4 clock disabled 1 (B_0x1): TIM4 clock enabled |
| TIM5EN | TIM5 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM5 clock disabled 1 (B_0x1): TIM5 clock enabled |
| TIM6EN | TIM6 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM6 clock disabled 1 (B_0x1): TIM6 clock enabled |
| TIM7EN | TIM7 clock enable This bit is set and cleared by software. 0 (B_0x0): TIM7 clock disabled 1 (B_0x1): TIM7 clock enabled |
| WWDGEN | WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 0 (B_0x0): WWDG clock disabled 1 (B_0x1): WWDG clock enabled |
| SPI2EN | SPI2 clock enable This bit is set and cleared by software. 0 (B_0x0): SPI2 clock disabled 1 (B_0x1): SPI2 clock enabled |
| USART2EN | USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USART2 clock disabled 1 (B_0x1): USART2 clock enabled |
| USART3EN | USART3 clock enable This bit is set and cleared by software. 0 (B_0x0): USART3 clock disabled 1 (B_0x1): USART3 clock enabled |
| UART4EN | UART4 clock enable This bit is set and cleared by software. 0 (B_0x0): UART4 clock disabled 1 (B_0x1): UART4 clock enabled |
| UART5EN | UART5 clock enable This bit is set and cleared by software. 0 (B_0x0): UART5 clock disabled 1 (B_0x1): UART5 clock enabled |
| I2C1EN | I2C1 clock enable This bit is set and cleared by software. 0 (B_0x0): I2C1 clock disabled 1 (B_0x1): I2C1 clock enabled |
| I2C2EN | I2C2 clock enable This bit is set and cleared by software. 0 (B_0x0): I2C2 clock disabled 1 (B_0x1): I2C2 clock enabled |
| CRSEN | CRS clock enable This bit is set and cleared by software. 0 (B_0x0): CRS clock disabled 1 (B_0x1): CRS clock enabled |
| USART6EN | USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 (B_0x0): USART6 clock disabled 1 (B_0x1): USART6 clock enabled |