PLL3P=B_0x0, PLL3Q=B_0x0, PLL3R=B_0x0
RCC PLL3 dividers configuration register
| PLL3N | Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). … … Others: reserved VCO output frequency = Fref3_ck x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: PLL3N between 4 and 512 input frequency Fref3_ck between 4 and 16MHz 3 (B_0x003): PLL3N = 4 4 (B_0x004): PLL3N = 5 5 (B_0x005): PLL3N = 6 128 (B_0x080): PLL3N = 129 (default after reset) 511 (B_0x1FF): PLL3N = 512 |
| PLL3P | PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_p_ck = vco3_ck 1 (B_0x1): pll3_p_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_p_ck = vco3_ck / 3 3 (B_0x3): pll3_p_ck = vco3_ck / 4 127 (B_0x7F): pll3_p_ck = vco3_ck / 128 |
| PLL3Q | PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_q_ck = vco3_ck 1 (B_0x1): pll3_q_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_q_ck = vco3_ck / 3 3 (B_0x3): pll3_q_ck = vco3_ck / 4 127 (B_0x7F): pll3_q_ck = vco3_ck / 128 |
| PLL3R | PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_r_ck = vco3_ck 1 (B_0x1): pll3_r_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_r_ck = vco3_ck / 3 3 (B_0x3): pll3_r_ck = vco3_ck / 4 127 (B_0x7F): pll3_r_ck = vco3_ck / 128 |