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STMicroelectronics /STM32U5Fx /DSI /DSI_VSCR

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Interpret as DSI_VSCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EN 0 (B_0x0)UR

UR=B_0x0, EN=B_0x0

Description

DSI Host video shadow control register

Fields

EN

Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated.

0 (B_0x0): Register update is disabled.

1 (B_0x1): Register update is enabled.
UR

Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared.

0 (B_0x0): No update requested

1 (B_0x1): Register update requested

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data