STMicroelectronics /STM32U5Fx /GFXTIM /GFXTIM_WDGTCR

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Interpret as GFXTIM_WDGTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)WDGEN 0 (B_0x0)WDGDIS 0 (B_0x0)WDGS 0 (B_0x0)WDGHRC 0 (B_0x0)WDGCS0 (B_0x0)FWDGR

WDGDIS=B_0x0, WDGCS=B_0x0, FWDGR=B_0x0, WDGHRC=B_0x0, WDGEN=B_0x0, WDGS=B_0x0

Description

GFXTIM watchdog timer configuration register

Fields

WDGEN

watchdog enable This bit enables the graphic watchdog.

0 (B_0x0): no effect

1 (B_0x1): graphic watchdog enabled

WDGDIS

watchdog disable This bit disables the graphic watchdog.

0 (B_0x0): no effect

1 (B_0x1): graphic watchdog disabled

WDGS

watchdog status This bit returns the status of the graphic watchdog.

0 (B_0x0): graphic watchdog disabled

1 (B_0x1): graphic watchdog enabled

WDGHRC

watchdog hardware reload configuration This field configures the watchdog hardware reload.

0 (B_0x0): watchdog hardware reload disabled

1 (B_0x1): watchdog reloaded a rising edge of gfxtim_wrld

2 (B_0x2): watchdog reloaded a falling edge of gfxtim_wrld

3 (B_0x3): reserved

WDGCS

watchdog clock source This field selects the watchdog clock source. others: reserved

0 (B_0x0): line clock

1 (B_0x1): frame clock

2 (B_0x2): HSYNC rising edge

3 (B_0x3): HSYNC falling edge

4 (B_0x4): VSYNC rising edge

5 (B_0x5): VSYNC falling edge

6 (B_0x6): TE rising edge

7 (B_0x7): TE falling edge

8 (B_0x8): event 1

9 (B_0x9): event 2

10 (B_0xA): event 3

11 (B_0xB): event 4

FWDGR

force watchdog reload This bit forces the reload of the graphic watchdog.

0 (B_0x0): no effect

1 (B_0x1): graphic watchdog reload forced

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