ODMAEN=B_0x0, IDMAEN=B_0x0, JCEN=B_0x0, EOCIE=B_0x0, OFNEIE=B_0x0, IFF=B_0x0, OFF=B_0x0, HPDIE=B_0x0, IFTIE=B_0x0, OFTIE=B_0x0, IFNFIE=B_0x0
JPEG control register
| JCEN | JPEG core enable This bit enables the JPEG codec core. 0 (B_0x0): Disabled (internal registers are reset). 1 (B_0x1): Enabled (internal registers are accessible). |
| IFTIE | Input FIFO threshold interrupt enable This bit enables interrupt generation when the input FIFO reaches a threshold. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IFNFIE | Input FIFO not full interrupt enable This bit enables interrupt generation when the input FIFO is not empty. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| OFTIE | Output FIFO threshold interrupt enable This bit enables interrupt generation when the output FIFO reaches a threshold. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| OFNEIE | Output FIFO not empty interrupt enable This bit enables interrupt generation when the output FIFO is not empty. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| EOCIE | End of conversion interrupt enable This bit enables interrupt generation at the end of conversion. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| HPDIE | Header parsing done interrupt enable This bit enables interrupt generation upon the completion of the header parsing operation. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IDMAEN | Input DMA enable Enables DMA request generation for the input FIFO. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| ODMAEN | Output DMA enable Enables DMA request generation for the output FIFO. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| IFF | Input FIFO flush This bit flushes the input FIFO. Note: Reads always return 0. 0 (B_0x0): No effect 1 (B_0x1): Input FIFO is flushed |
| OFF | Output FIFO flush This bit flushes the output FIFO. Note: Reads always return 0. 0 (B_0x0): No effect 1 (B_0x1): Output FIFO is flushed |