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STMicroelectronics /STM32W108 /CLK /CLK_PERIODCR

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Interpret as CLK_PERIODCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MODE

Description

Clock period control register

Fields

MODE

Sets clock to be measured by CLK_PERIOD

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data