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STMicroelectronics /STM32W108 /GPIOA /GPIOA_ODR

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Interpret as GPIOA_ODR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ODR0)ODR0 0 (ODR1)ODR1 0 (ODR2)ODR2 0 (ODR3)ODR3 0 (ODR4)ODR4 0 (ODR5)ODR5 0 (ODR6)ODR6 0 (ODR7)ODR7

Description

Port A output data register

Fields

ODR0

ODR0
ODR1

ODR1
ODR2

ODR2
ODR3

ODR3
ODR4

ODR4
ODR5

ODR5
ODR6

ODR6
ODR7

ODR7

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data