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STMicroelectronics /STM32W108 /TIM1 /TIM1_SMCR

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Interpret as TIM1_SMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMS0TS0 (MSM)MSM 0ETF0ETPS 0 (ECE)ECE 0 (ETP)ETP

Description

slave Mode Control register

Fields

SMS

SMS
TS

TS
MSM

MSM
ETF

ETF
ETPS

ETPS
ECE

ECE
ETP

ETP

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data