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SiFive /FE310 /GPIO0 /output_en

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Interpret as output_en

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (pin0)pin0 0 (pin1)pin1 0 (pin2)pin2 0 (pin3)pin3 0 (pin4)pin4 0 (pin5)pin5 0 (pin6)pin6 0 (pin7)pin7 0 (pin8)pin8 0 (pin9)pin9 0 (pin10)pin10 0 (pin11)pin11 0 (pin12)pin12 0 (pin13)pin13 0 (pin14)pin14 0 (pin15)pin15 0 (pin16)pin16 0 (pin17)pin17 0 (pin18)pin18 0 (pin19)pin19 0 (pin20)pin20 0 (pin21)pin21 0 (pin22)pin22 0 (pin23)pin23 0 (pin24)pin24 0 (pin25)pin25 0 (pin26)pin26 0 (pin27)pin27 0 (pin28)pin28 0 (pin29)pin29 0 (pin30)pin30 0 (pin31)pin31

Description

Pin Output Enable Register

Fields

pin0
pin1
pin2
pin3
pin4
pin5
pin6
pin7
pin8
pin9
pin10
pin11
pin12
pin13
pin14
pin15
pin16
pin17
pin18
pin19
pin20
pin21
pin22
pin23
pin24
pin25
pin26
pin27
pin28
pin29
pin30
pin31

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data