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SiFive /FE310 /I2C0 /cr

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Interpret as cr

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (iack)iack 0 (ack)ack 0 (wr)wr 0 (rd)rd 0 (sto)sto 0 (sta)sta

ack=ack

Description

Command register

Fields

iack

Interrupt acknowledge. When set, clears a pending interrupt
ack

When a receiver, sent ACK (0) or NACK (1)

0 (ack): undefined

1 (nack): undefined
wr

Write to slave
rd

Read from slave
sto

Generate stop condition
sta

Generate (repeated) start condition

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data