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SiFive /FE310 /I2C0 /sr

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Interpret as sr

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (if)if 0 (tip)tip 0 (al)al 0 (busy)busy 0 (rx_ack)rx_ack

Description

Status register

Fields

if

Interrupt Flag. This bit is set when an interrupt is pending, which will cause a processor interrupt request if the IEN bit is set.
tip

Transfer in progress
al

Arbitration lost
busy

I2C bus busy
rx_ack

Received acknowledge from slave. This flag represents acknowledge from the addressed slave. ‘1’ = No acknowledge received ‘0’ = Acknowledge received

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data