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SiFive /FE310 /PRCI /pllcfg

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Interpret as pllcfg

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (R1)pllr0pllf0pllq 0 (sel)sel 0 (refsel)refsel 0 (bypass)bypass 0 (lock)lock

pllr=R1

Description

PLL Configuration Register

Fields

pllr

0 (R1): undefined

1 (R2): undefined

2 (R3): undefined

3 (R4): undefined
pllf
pllq

1 (Q2): undefined

2 (Q4): undefined

3 (Q8): undefined
sel
refsel
bypass
lock

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data